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M34A02
2 Kbit Serial SMBus EEPROM for ACR Card Configuration
PRODUCT PREVIEW
s s s s s s s s s s
Two Wire SMBus Serial Interface 2.7V to 3.6V Single Supply Voltage Hardware Write Control BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
8 1
SO8 (MN) 150 mil width
DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits, and operate down to 2.7 V. These devices are available in Plastic Small Outline and Thin Shrink Small Outline packages. These devices are written by the ACR card-issuer, and then accessed in Read mode in the application, using the ACR Serial Bus protocol. This is a two wire serial interface that uses a bidirectional data bus and serial clock. The device carries a built-in 4-bit Device Type Identifier code (1011). The device behaves as a slave in the ACR Serial Bus protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition
8 1
TSSOP8 (DW) 169 mil width
Figure 1. Logic Diagram
VCC
3 E0-E2 SDA M34A02
Table 1. Signal Names
E0, E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
SCL WC
VSS
AI03794
April 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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Figure 2. SO and TSSOP Connections Figure 3. Typical ACR Application PCB Connection (showing E2,E1,E0 address 000)
VCC M34A02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI03795
E0 VCC WC SCL SDA E1 E2 VSS VSS
VCC WC SCL SDA RL
ACR Bus
AI04092
Note: 1. This arrangement on the chip enable lines allows the application to start at ACR address 000h.
is followed by a Device Select code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage
threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 3 indicates how the value of the pull-up resistor
Value -40 to 125 -65 to 150
Unit C C C V V V
SO8: 20 seconds (max) 2 TSSOP8: 20 seconds (max) 2
235 235 -0.6 to 6.5 -0.3 to 6.5 4000
Electrostatic Discharge Voltage (Human Body model) 3
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs should be tied to V CC or VSS, to establish the Device Select Code. Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent erase and write operations. Write operations are disabled to the entire memory array when Write Control (WC) is held High. When unconnected, the signal is internally read as V IL, and Write operations are allowed. When Write Control (WC) is held High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. DEVICE OPERATION The device supports the ACR Serial Bus protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of the SDA line while the clock SCL is stable in the High state. A Stop condition terminates communication between the device and the bus master. A Stop condition at the end of a Read command, provided that it is followed by NoAck, forces the device into its Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).
Figure 4. Maximum R L Value versus Bus Capacitance (CBUS) for an ACR Serial Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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Figure 5. ACR Serial Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
For correct device operation, Serial Data (SDA) must be stable before the rising edge of Serial Clock (SCL), and the data must change only after Serial Clock (SCL) is Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the 8-bit byte, shown in Table 3, on Serial Data (SDA) (most significant bit first). This
consists of the 7-bit Device Select code, and the Read/Write bit (RW). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1011b. Up to eight memory devices can be connected on a single bus. Each one is given a unique 3-bit code on Chip Enable (E0, E1, E2). When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Select Code is the
Table 3. Device Select Code 1
Device Type Identifier b7 Device Select Code 1 b6 0 b5 1 b4 1 b3 E2 Chip Enable b2 E1 b1 E0 RW b0 RW
Note: 1. The most significant bit, b7, is sent first.
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Table 4. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = 0
16
START, Device Select, RW = 0
same as the pattern applied on Chip Enable (E0, E1, E2). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC ACK Byte Write START DEV SEL R/W ACK NO ACK DATA IN STOP ACK NO ACK DATA IN 1
BYTE ADDR
WC ACK Page Write START DEV SEL R/W NO ACK DATA IN 3
BYTE ADDR
DATA IN 2
WC (cont'd) NO ACK Page Write (cont'd) NO ACK
DATA IN N STOP
AI02803C
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Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC ACK BYTE WRITE START DEV SEL R/W ACK DATA IN STOP ACK DATA IN 1 ACK DATA IN 2 ACK
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W ACK DATA IN 3
BYTE ADDR
WC (cont'd)
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
AI02804
Write Operations Following a Start condition the bus master sends a Device Select code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 6, and waits for one address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is taken High. Any Write instruction with Write Control (WC) held High (during a period of time from the Start condition until the end of the address byte) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 5. Each data byte in the memory has a 8-bit address. When the bus master generates a Stop condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time does not trigger the internal Write cycle.
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During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests (and sends NoAck in reply to them). Byte Write After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC), the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 6. Page Write The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits (b7-b4) are the same. If more bytes are sent than will fit up to the end of the row, a condition known
M34A02
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
as `roll-over' occurs. Data starts to become overwritten (in a way not formally specified in this data sheet). The bus master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 4 least significant bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 6, but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: - Initial condition: a Write cycle is in progress. - Step 1: the bus master issues a Start condition followed by a Device Select code (the first byte of the new instruction). - Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the Write Control (WC) signal.
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Figure 9. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 3rd bytes) must be identical.
Random Address Read A dummy Write is performed to load the address into the address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the
Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the byte. Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte
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Table 5. DC Characteristics (TA = -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol ILI ILO ICC ICC1 VIL VIH VIL VIH VOL Parameter Input Leakage Current (SCL, SDA, E2, E1, E0) Output Leakage Current Supply Current VCC =2.7V, fc=100kHz (rise/fall time < 30ns) Supply Current (Stand-by) Input Low Voltage (E0-E2, SCL, SDA) Input High Voltage (E0-E2, SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC) Output Low Voltage IOL = 3 mA VIN = VSS or VCC - 0.3 2.1 - 0.3 2.1 1 1 0.8 VCC+1 0.5 VCC+1 0.4 mA A V V V V V Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC=3.6V, fc=100kHz (rise/fall time < 30ns) Min. Max. 2 2 2 Unit A A mA
Table 6. AC Characteristics
M34A02 Symbol Alt. Parameter VCC=2.7 to 3.6V TA = -40 to 85C Min tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tCHCL tCLCH tCHDX 1 tDLCL tDXCX tCLDX tCHDH tDHDL tCLQV 3 tCLQX fC tW tR tF tR tF tHIGH tLOW tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock Pulse Width High Clock Pulse Width Low START Set-up Time START Hold Time SDA In Set-up Time SDA In Hold Time STOP Set-up Time Time the bus must be free between STOP and next START Clock Low to SDA Out Valid SDA Out Hold Time after Clock Low Clock Frequency Write Time 4 4.7 4.7 4 250 0 4 4.7 400 300 10 100 10 900 Max 1000 300 1000 300 ns ns ns ns s s s s ns s s s ns ns kHz ms Unit
Note: 1. For a reStart condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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Figure 10. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages <= 50 ns 0.4V to 2.3V 0.8V to 2.1V 0.4V 0.8V
AI03799
2.3V
2.1V
Table 7. Input Parameters1 (TA = 25 C, f = 100 kHz)
Symbol CIN CIN ZWCL ZWCH tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.5 V VIN > 0.7VCC Single glitch 5 500 100 Test Condition Min. Max. 8 6 70 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested.
Figure 11. AC Waveforms
tCHCL tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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Table 8. Ordering Information Scheme
Example: M34A02 - V DW 6 T
Memory Capacity 02 2 Kbit (256 x 8) T
Option Tape and Reel Packing
Operating Voltage V 2.7 V to 3.6 V
Package MN DW SO8 (150 mil width) TSSOP8 (169 mil width) 6
Temperature Range -40 C to 85 C
output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode. ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh).
The notation used for the device number is as shown in Table 8. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M34A02
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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TSSOP8 - 8 lead Thin Shrink Small Outline
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
B
e TSSOP
Note: 1. Drawing is not to scale.
TSSOP8 - 8 lead Thin Shrink Small Outline
mm Symb. Typ. A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8 inches
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Table 9. Revision History
Date 19-Sep-2000 14-Mar-2001 20-Apr-2001 Rev. 1.0 1.1 1.2 Document written Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to I2C changed to ACR Serial Bus Description of Revision
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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